Characterizing finite Kripke structures in propositional temporal logic
Theoretical Computer Science - International Joint Conference on Theory and Practice of Software Development, P
Symbolic model checking for real-time systems
Information and Computation
Symbolic Model Checking
Introduction to Algorithms
Automata For Modeling Real-Time Systems
ICALP '90 Proceedings of the 17th International Colloquium on Automata, Languages and Programming
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Improving the Verification of Timed Systems Using Influence Information
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Partial Order Reductions for Timed Systems
CONCUR '98 Proceedings of the 9th International Conference on Concurrency Theory
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Reducing the number of clock variables of timed automata
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Efficient verification of real-time systems: compact data structure and state-space reduction
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Static Analysis for State-Space Reductions Preserving Temporal Logics
Formal Methods in System Design
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Slicing of Timed Automata with Discrete Data
Fundamenta Informaticae - SPECIAL ISSUE ON CONCURRENCY SPECIFICATION AND PROGRAMMING (CS&P 2005) Ruciane-Nide, Poland, 28-30 September 2005
Static guard analysis in timed automata verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
√erics: a tool for verifying timed automata and estelle specifications
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper presents a method of abstraction for timed systems. Toextract an abstract model of a timed system we propose to usestatic analysis, namely a technique called path compression. Theidea behind the path compression consists in identifying a path (ora set of paths) on which a process executes a sequence oftransitions that do not influence a property being verified, andreplacing this path with a single transition. The method isproperty driven since it depends on a formula in question. Theabstraction is exact with respect to all the properties expressiblein the temporal logic CTL^*_{-X}.