Asynchronous computing in sense amplifier-based pass transistor logic

Authors:
Tsung-Te Liu;Louis P. Alarcón;Matthew D. Pierson;Jan M. Rabaey
Affiliations:
Berkeley Wireless Research Center, University of California, Berkeley, CA;Berkeley Wireless Research Center, University of California, Berkeley, CA;Berkeley Wireless Research Center, University of California, Berkeley, CA;Berkeley Wireless Research Center, University of California, Berkeley, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.