Statistical static timing analysis considering leakage variability in power gated designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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A model for process-induced parameter variations is proposed, combining die-to-die, within-die systematic, and within-die random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of within-die correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a "generic" critical path, leading to what is referred to as a "process-specific" statistical-timing-analysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are "full-chip," applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design