Intel LVS logic as a combinational logic paradigm in CNT technology

Authors:
Bao Liu;Zhen Cao;Jun Tao;Xuan Zeng;Pushan Tang;Philip H.-S. Wong
Affiliations:
The University of Texas, San Antonio, TX;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China;Stanford University, Stanford, CA
Venue:
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Year:
2010

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Abstract

In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, transmission gate logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44x) performance improvement and (e.g., 3.83x) power consumption reduction, while transmission gate logic and Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02x performance improvement and 1137.64x power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.