On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Closed-form solution for timing analysis of process variations on SWCNT interconnect
Proceedings of the 11th international workshop on System level interconnect prediction
Intel LVS logic as a combinational logic paradigm in CNT technology
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
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In this paper, we investigate the impact of process variations on future interconnect solutions based on single-walled carbon nanotubes (SWCNT) bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall 3-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by 63% in 22 nm process technology.