ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Warning Prediction Sequential for Transient Error Prevention
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a construction of timing-error-detecting dual-edge-triggered flip-flops (DET-FFs). The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with relatively large area, the proposed FF uses internal signals in a DET-FF as as an alternative to the transition detector. This paper also shows an evaluation result indicating that the proposed FF has smaller area overhead than the simple combination of the conventional DET-FF and timing error detection methods.