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TIMBER: time borrowing and error relaying for online timing error resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Run-time adaptive performance compensation using on-chip sensors
Proceedings of the 16th Asia and South Pacific Design Automation Conference
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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Proceedings of the Conference on Design, Automation and Test in Europe
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Journal of Electronic Testing: Theory and Applications
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The deep submicron (DSM) semi-conductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case design. It is easier to design than the previously proposed Razor logic by eliminating delayed clock. Estimates based on gate-level simulations show that the canary logic achieves average power reduction of 30% by exploiting dynamic variations in circuit delay.