Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction

Authors:
Hiroshi Fuketa;Masanori Hashimoto;Yukio Mitsuyama;Takao Onoye
Affiliations:
Osaka University, Japan and JST, CREST;Osaka University, Japan and JST, CREST;Osaka University, Japan and JST, CREST;Osaka University, Japan and JST, CREST
Venue:
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Year:
2009

Citing 1
Cited 3

A Simple Flip-Flop Circuit for Typical-Case Designs for DFM

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits

Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Run-time adaptive performance compensation using on-chip sensors

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Timing margin of a chip varies chip by chip due to manufacturing variability, and depends on operating environment and aging. Adaptive speed control with timing error prediction is a promising approach to mitigate the timing margin variation, whereas it inherently has a critical risk of timing error occurrence when a circuit is slowed down. This paper presents how to evaluate the relation between timing error rate and power dissipation in self-adaptive circuits with timing error prediction. The discussion is experimentally validated using a 32-bit ripple carry adder in subthreshold operation in a 90nm CMOS process. We show a trade-off between timing error rate and power dissipation, and reveal the dependency of the trade-off on design parameters.