A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Aging test strategy and adaptive test scheduling for SoC failure prediction
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper discusses run-time adaptive performance control with on-chip sensors that predict timing errors. The sensors embedded into functional circuits capture delay variations due to not only die-to-die process variation but also random process variation, environmental fluctuation and aging. By compensating circuit performance according to the sensor outputs, we can overcome PVT worst-case design and reduce power dissipation while satisfying circuit performance. We applied the adaptive speed control to subthreshold circuits that are very sensitive to random variation and environmental fluctuation. Measurement results of a 65nm test chip show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding.