A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

Authors:
Wai Chung;T. Lo;M. Sachdev
Affiliations:
Electr. & Comput. Eng. Dept., Univ. of Waterloo, Ont., Canada;-;-
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop

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Abstract

This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.