Modeling and analysis of circuit performance of ballistic CNFET

Authors:
Bipul C. Paul;Shinobu Fujita;Masaki Okajima;Thomas Lee
Affiliations:
Stanford University, Stanford, CA and Toshiba America Research Inc., San Jose, CA;Toshiba America Research Inc., San Jose, CA;Toshiba America Research Inc., San Jose, CA;Stanford University, Stanford, CA
Venue:
Proceedings of the 43rd annual Design Automation Conference
Year:
2006

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Abstract

With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.