Predictive technology model for nano-CMOS design exploration
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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The minimum feature size of CMOS technology will reach 10nm in ten years. Beyond that benchmark, the present scaling approach may have to take a different route. The grand challenge to integrated circuit design community is to identify alternative technologies, such as carbon-based electronics, integrate them into the circuit architecture, and enable continuous growth of chip scale and performance. Predictive Technology Model (PTM), which bridges the process development and circuit simulation through device modeling, is essential in assessing potentials and limits of new technology and in supporting early design prototyping.