Carbon nanotube transistor compact model for circuit design and performance optimization
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Techniques for leakage energy reduction in deep submicrometer cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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This paper presents a performance comparison of a carbon nanotube-based field effect (CNFET)- and CMOS-based 6T SRAM cell at the 32nm technology node. HSPICE simulations, carried out using Berkeley predictive technology model (BPTM), show that for a cell ratio and pull-up ratio of 1, CNFET-based 6T SRAM cell provides an improvement of 21% in read static noise margin (SNM) at VDD=0.4V. The speed of CNFET cell is 1.84x that of CMOS cell. The standby leakage of CNFET cell is 84% less than CMOS cell. The process parameter variation results in 1.2% change in the read SNM of CNFET cell as compared with a wide variation of around 10.6% in CMOS cell.