Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2007 international workshop on System level interconnect prediction
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
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As resistivity of Copper (Cu) increases with technology scaling, this drives us to look for new interconnect material for future very large scale integration (VLSI). Mixed carbon nanotube (CNT) bundle has superior properties like current carrying capacity and conductivity than Cu interconnect. It is the mixture of single wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) due to the nature of the bottom-up fabrication process. In this paper, impact on resistance of the bundle has been shown due to various process parameters of the bundle and then optimized values of those parameters have been given. This work also presents a comprehensive analysis of bundle and compares its resistance (R) with those of the Cu interconnects for intermediate and global interconnect levels for 32nm technology node. More reduction in bundle resistance has been achieved than the research work reported in literature. The result show that bundle has smaller values of R compared to its Cu interconnect counterparts. This is advantageous for VLSI interconnect design and performance.