Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Are carbon nanotubes the future of VLSI interconnections?
Proceedings of the 43rd annual Design Automation Conference
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology
On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects
IEEE Transactions on Nanotechnology
Electrothermal Characterization of Single-Walled Carbon Nanotube (SWCNT) Interconnect Arrays
IEEE Transactions on Nanotechnology
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The performance of Single-Wall Carbon Nanotube (SWCNT) based interconnect is investigated in this paper. CNT has become the most promising replacement for Cu based interconnects in future VLSI technologies in the nanometer regime. The process, temperature, and voltage (PTV) dependent equivalent circuit model for CNT based interconnect is developed. The performances of Cu and CNT based interconnects are compared for different ITRS technology nodes. The timing delay is analyzed in CNT based interconnect under different PTV conditions for 32 nm and 16 nm technology nodes. Process variation is modeled by considering the variations in CNT diameter, spacing, and metallic fraction. The delay variation is more than 100 % with process variation whereas with voltage and temperature the delay variations are 卤20 % and 卤50---60 % from the nominal voltage and room temperature, respectively. The diameter variation of CNT has almost no effect on the timing of SWCNT bundle based interconnects.