Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Single-walled carbon nanotube electronics
IEEE Transactions on Nanotechnology
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes
IEEE Transactions on Nanotechnology
Ultra-low-power signaling challenges for subthreshold global interconnects
Integration, the VLSI Journal
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
| Hi-index | 0.00 |
The work in this paper addresses the need to evaluate the impact of emerging interconnect technologies, such as carbon nanotubes (CNTs), in the context of system applications. The critical properties of CNTs are described in terms of equivalent material parameters such that a general methodology of interconnect sizing can be used. This methodology is used to rescale the interlayer dielectric (ILD) stack-up and wire dimensions for different combinations of CNT and copper interconnects and vias; the stack-ups are then examined in an on-chip network application. The results of changing the ILD and wire sizing for a conservative estimate assuming a CNT bundle with 1/3 contacted metallic CNTs showed 30% improvement in delay and energy over copper at the 22 nm node and a 50% increase in total system throughput for a power constrained on-chip network application.