NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanocell logic gates for molecular computing
IEEE Transactions on Nanotechnology
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
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Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process technology continues to scale, standard copper interconnect will become a major bottleneck for FPGA performance. In this paper, we propose utilizing bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric and compare their performance to standard copper interconnect in future process technologies. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the segmentation distribution and the internal population of the wires. The results demonstrate that FPGAs utilizing SWCNT bundle interconnect can achieve a 19% improvement in average area delay product over the best performing architecture for standard copper interconnect in 22 nm process technology.