Analytical Model for the CMOS Short-Circuit Power Dissipation

Authors:
L. Bisdounis;S. Nikolaidis;O. Koufopavlou
Affiliations:
VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece;Electronics & Computers Division, Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece;VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece
Venue:
Integrated Computer-Aided Engineering
Year:
1998

Citing 3
Cited 1

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Principles of CMOS VLSI design: a systems perspective
A unified design methodology for CMOS tapered buffers

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Explicit evaluation of short circuit power dissipation for CMOS logic structures

ISLPED '95 Proceedings of the 1995 international symposium on Low power design

Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

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Abstract

A significant part of the power dissipation in CMOS digital circuits is due to the short-circuit currents. In this paper an accurate analytical model for the evaluation of the CMOS short-circuit power dissipation, on the basis of a CMOS inverter, is presented. The innovation of the proposed approach against previous works is due to the accurate, analytical expressions of the inverter output waveform which include for the first time the effects of both transistor currents and the gate-to-drain coupling capacitance. The α-power law MOS model which considers the carriers' velocity saturation effects of short-channel devices is used. The results produced by the suggested model show very good agreement with SPICE simulations.