A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2004 international symposium on Low power electronics and design
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An integrated switched-capacitor (SC) DC-DC converter with a digital interleaving regulation scheme is presented. By interleaving the newly-structured charge pump (CP) subcells in multiple phases, the input current ripple and output voltage ripple of the converter are reduced significantly. The converter exhibits excellent robustness, even when one CP sub-cell fails to operate due to unexpected device failure. A fully digital controller is employed with hysteretic control, featuring deadbeat stability and fast transient response. With a 1.5-V input power supply, the SC power converter precisely provides an adaptable regulated power output from 1.6 to 2.7 V. A maximum output ripple of ±20 mV is observed at the full load of 540 mW. The load transient response is around 1.8 µs, when the load current switches from half to full load (from 100 to 200 mA). The design provides a fast-response, low-noise, and fault-tolerant solution to new-generation on-chip power supplies.