Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation

Authors:
Chuang Zhang;Dongsheng Ma;Ashok Srivastava
Affiliations:
Louisiana State University, Baton Rouge, LA;University of Arizona, Tucson, AZ;Louisiana State University, Baton Rouge, LA
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

Citing 3
Cited 4

Embedded power supply for low-power DSP

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design issues for dynamic voltage scaling

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Voltage scheduling in the IpARM microprocessor system

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

Robust multiple-phase switched-capacitor DC-DC power converter with digital interleaving regulation scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An integrated switching DC-DC converter with dual-mode pulse-train/PWM control

IEEE Transactions on Circuits and Systems II: Express Briefs
Integrated interleaving SC power converters with analog and digital control schemes for energy-efficient microsystems

Analog Integrated Circuits and Signal Processing
Enabling power-efficient DVFS operations on silicon

IEEE Circuits and Systems Magazine

Quantified Score

Hi-index	0.00

Visualization

Abstract

Dynamic voltage scaling (DVS) is a very effective low-power design technique in modern digital IC systems. On-chip adaptive DC/DC converter, which provides adjustable output voltage, is a key component in implementing DVS-enabled system. This paper presents a new adaptive DC/DC converter design, which adopts a delay-line controller for voltage regulation. With a proposed adaptive pulse-train technique, ripple voltages are reduced by 50%, while the converter still maintains satisfying transient response. With a supply voltage of 3.3V, the output of the converter is well regulated from 1.7 to 3.0V. Power consumption of the controller is below 100mW. Maximum efficiency of 92% is achieved with output power of 125mW. Chip area is 0.8 x 1.2mm2 in 1.5µm standard CMOS process.