Proceedings of the 2004 international symposium on Low power electronics and design
Enabling power-efficient DVFS operations on silicon
IEEE Circuits and Systems Magazine
Analog Integrated Circuits and Signal Processing
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This paper addresses design strategies and tradeoffs of a series of newly developed interleaving switched-capacitor power converters. In such a design, a converter consists of multiple sub-cells in the power stage, and is regulated with interleaving power flow control. By splitting the power flow in a time-sequenced manner, the converter maintains a continuous power delivery flow to the output V OUT, with significant reductions on the in-rush input current and the output voltage ripples. System modeling and optimization focusing on power efficiency and z-domain closed-loop gain enhancement are discussed. An experimental prototype was successfully fabricated with a standard 0.35-μm digital CMOS N-well process. The entire die area, including fully integrated pads and power devices, is 3.84 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load of 250 mA, the output of the converter is well regulated at 2.5 V with 16-mV ripple. The maximum efficiency of 82.3% is achieved at the output power of 625 mW.