Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
Shaping a VLSI wire to minimize delay using transmission line model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes
Microelectronic Engineering
Design Challenges of Technology Scaling
IEEE Micro
Shaping a VLSI Wire to Minimize Elmore Delay
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire width planning for interconnect performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect modeling for improved system-level design optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
E-beam lithography stencil planning and optimization with overlapped characters
Proceedings of the 2011 international symposium on Physical design
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For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physics-based models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closed-form scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70% underestimation of the delay, or 20x oversizing. We also obtain the new closed-form wiresizing functions with consideration of scattering effects.