Accurate predictive interconnect modeling for system-level design

Authors:
Luca P. Carloni;Andrew B. Kahng;Swamy V. Muddu;Alessandro Pinto;Kambiz Samadi;Puneet Sharma
Affiliations:
Department of Computer Science, Columbia University at New York, NY;Department of Computer Science and Engineering and the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;AMD, Sunnyvale, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA;Freescale Semiconductor, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

We propose new accurate predictive models for the delay, power, and area of buffered interconnects to enable a more effective system-level design exploration with existing and future nanometer technology processes. We show that our models are significantly more accurate than previous models--essentially matching sign-off analyses. We integrate our models in the COSI-OCC communication synthesis infrastructure and show how they impact the feasibility and optimality of the network-on-chip architectures that are synthesized by this tool.