Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Timing and crosstalk driven area routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
River PLAs: a regular circuit structure
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design Methodology for a 1.0 GHz Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Power minimization for dynamic PLAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Nanotechnology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing with crosstalk constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk alleviation for dynamic PLAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a maximum crosstalk effect minimization algorithm that takes logic synthesis into consideration for PLA structures. To minimize the crosstalk effect, a technique for permuting wire is used which contains the following steps. First, product terms are partitioned into long and short sets, and then the product terms in the long and short sets are interleaved. After that, we take advantage of the crosstalk immunity of product terms in the long set to further reduce the maximum coupling capacitance of the PLA. Finally, synthesis techniques such as local and global transformations are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum coupling capacitance of a circuit by 51% as compared with the original area-minimized PLA without crosstalk effect minimization.