A novel VLSI layout fabric for deep sub-micron applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
River PLAs: a regular circuit structure
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk alleviation for dynamic PLAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a maximum crosstalk minimization algorithm taking logic synthesis into consideration for PLA structure. To minimize the crosstalk, technique of permuting wire is used which includes the following steps. First, product lines are partitioned into long set and short set, and then product lines in long set and short set are interleaved. By interleaving algorithm, an upper bound on the maximum coupling capacitance of the product lines can be derived.Then, we take advantage of crosstalk immunity of product lines in long set to further reduce the maximum crosstalk effect of the PLA. Finally, synthesis techniques such as local transformation and global transformation are taken into consideration to search for a better result. The experiments demonstrate that our algorithm can effectively minimize the maximum crosstalk effect of a circuit by 48% as compared with the original area-minimized PLA without crosstalk minimization.