Energy-efficient redundant execution for chip multiprocessors

Authors:
Pramod Subramanyan;Virendra Singh;Kewal K. Saluja;Erik Larsson
Affiliations:
Indian Institute of Science, Bangalore, India;Indian Institute of Science, Bangalore, India;University of Wisconsin-Madison, Bangalore, WI, India;Linkoping University, Linkoping, Sweden
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.