Transient fault detection via simultaneous multithreading
Proceedings of the 27th annual international symposium on Computer architecture
Detailed design and evaluation of redundant multithreading alternatives
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
ReStore: Symptom-Based Soft Error Detection in Microprocessors
IEEE Transactions on Dependable and Secure Computing
| Hi-index | 0.00 |
In this paper, we investigate techniques to incorporate fault tolerance in superscalar processors, the de facto execution model for building processors today. We first analyze the different ways in which errors can manifest when faults occur in various parts of a superscalar processor. We then describe different ways of detecting and recovering from these errors, and the merits and demerits of these schemes. Finally, we present the results of a simulation study conducted to determine the performance loss incurred due to the introduction of these fault tolerance schemes. These results suggest that fault tolerance can be incorporated in superscalar processors, with low hardware overhead, low performance overhead, and good error coverage.