Reducing parity generation latency through input value aware circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting inactive rename slots for detecting soft errors
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Proceedings of the 49th Annual Design Automation Conference
Combating NBTI-induced aging in data caches
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors in a processor. Our designs are generally motivated by the fact that many of the produced and consumed values in the processors are narrow and their upper order bits are meaningless. Soft errors caused by any particle strike to these higher order bits can be avoided by simply identifying these narrow values. Alternatively, soft errors can be detected or corrected on the narrow values by replicating the vulnerable portion of the value inside the storage space provided for the upper order bits of these operands. We offer a variety of schemes that make use of narrow values and analyze their efficiency in reducing soft error vulnerability of level-0 data cache of the processor.