Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Computing Architectural Vulnerability Factors for Address-Based Structures
Proceedings of the 32nd annual international symposium on Computer Architecture
Computing Cache Vulnerability to Transient Errors and Its Implication
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Exploiting Narrow Values for Soft Error Tolerance
IEEE Computer Architecture Letters
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
Penelope: The NBTI-Aware Processor
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors
IEEE Transactions on Computers
Dynamic indexing: concurrent leakage and aging optimization for caches
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Investigating the impact of NBTI on different power saving cache strategies
Proceedings of the Conference on Design, Automation and Test in Europe
Combating Aging with the Colt Duty Cycle Equalizer
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Aging-Aware Instruction Cache Design by Duty Cycle Balancing
ISVLSI '12 Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI
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The negative bias temperature instability (NBTI) in CMOS devices is one of most prominent sources of aging mechanisms, which can induce severe threats to the reliability of modern processors at deep submicron semiconductor technologies. Due to the unbalanced duty cycle ratio of the SRAM cells, the data cache suffers a heavy NBTI stress and this will further exacerbate the aging effect in the data cache. In this paper, an aging-aware design is proposed to combat the NBTI-induced aging in the data cache. First, the detailed lifetime behaviors of the cachelines in the data cache are studied. Then, different schemes are proposed to mitigate the negative aging effects by balancing the duty cycle ratio of the SRAM cells in the cachelines according to their different lifetime phases. By applying our proposed idle-time-based cacheline invalidation, early write-back, and bit-flipping schemes, the duty cycle ratio of the data cache can be well balanced. By adopting the drowsy scheme for invalidated cachelines, our design can also reduce the power consumption significantly, which will further optimize the thermal behavior and aging effect of data caches.