Area efficient architectures for information integrity in cache memories
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Essentials of Error-Control Coding Techniques
Essentials of Error-Control Coding Techniques
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Transient Fault Tolerance in Digital Systems
IEEE Micro
IBM's S/390 G5 Microprocessor Design
IEEE Micro
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Soft error and energy consumption interactions: a data cache perspective
Proceedings of the 2004 international symposium on Low power electronics and design
The Soft Error Problem: An Architectural Perspective
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability
IEEE Transactions on Computers
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Future cache memories must deal with soft errors to ensure data reliability. This paper investigates the addition of a small cache – replica victim cache, to accommodate the replicas that are frequently evicted from the L1 data cache due to in-cache replication (ICR) for further enhancing the data reliability against soft errors. Our experimental results reveal that a replica victim cache with only four entries can increase the reliability of the L1 data cache by 21.7% more than ICR without impacting performance significantly. Also, the area overhead is less than 10% for most L1 data cache configurations. We believe the proposed scheme provides an interesting cache design option, especially for the applications that are operated in highly noisy environments or demand very high data integrity.