ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
IBM's S/390 G5 Microprocessor Design
IEEE Micro
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
The architecture of Tandem's NonStop system
ACM '81 Proceedings of the ACM '81 conference
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the conference on Design, automation and test in Europe
REPAS: Reliable Execution for Parallel ApplicationS in Tiled-CMPs
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
Architecture Design for Soft Errors
Architecture Design for Soft Errors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast online error detection and correction with thread signature calculae
Microprocessors & Microsystems
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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Fingerprinting summarizes the history of internal processor state updates into a cryptographic signature. The processors in a dual modular redundant pair periodically exchange and compare fingerprints to corroborate each other's correctness. relative to other techniques, fingerprinting offers superior error coverage and significantly reduces the error-detection latency and bandwidth.