Fingerprinting: bounding soft-error detection latency and bandwidth
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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In this paper we propose1 a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (Flip-Flops) of the duplicated system are implemented as multi-mode memory elements according to [9] allowing during normal operation to accumulate a signature of its states in its scan-paths. By continously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.