Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rodinia: A benchmark suite for heterogeneous computing
IISWC '09 Proceedings of the 2009 IEEE International Symposium on Workload Characterization (IISWC)
Dynamic warp subdivision for integrated branch and memory divergence tolerance
Proceedings of the 37th annual international symposium on Computer architecture
Energy-efficient mechanisms for managing thread context in throughput processors
Proceedings of the 38th annual international symposium on Computer architecture
IEEE Transactions on Computers
Energy-Aware Workload Consolidation on GPU
ICPPW '11 Proceedings of the 2011 40th International Conference on Parallel Processing Workshops
Run-time power-gating in caches of GPUs for leakage energy savings
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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GPUs spend significant time on synchronization stalls. Such stalls provide ample opportunity to save leakage energy in GPU structures left idle during such periods. In this paper we focus on the register file structure of NVIDIA GPUs and introduce sync-aware low leakage solutions to reduce power. Accordingly, we show that applying the power gating technique to the register file during synchronization stalls can improve power efficiency without considerable performance loss. To this end, we equip the register file with two leakage power saving modes with different levels of power saving and wakeup latencies.