Efficient design space exploration in PICO
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Conjoined-Core Chip Multiprocessing
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Instruction set extension with shadow registers for configurable processors
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Automatic Synthesis of System on Chip Multiprocessor Architectures for Process Networks
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Proceedings of the 32nd annual international symposium on Computer Architecture
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The microarchitecture of FPGA-based soft processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
A field programmable gate array media player for realmedia files
Journal of Computing Sciences in Colleges
A stream chip-multiprocessor for bioinformatics
ACM SIGARCH Computer Architecture News
MB-LITE: a robust, light-weight soft-core implementation of the MicroBlaze architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Improving Floating-Point Performance in Less Area: Fractured Floating Point Units (FFPUs)
Journal of Signal Processing Systems
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Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors.