Modeling the effects of DFS on power consumption in hybrid chip multiprocessors

  • Authors:
  • Ami Marowka

  • Affiliations:
  • Bar-Ilan University, Ramat Gan, Israel

  • Venue:
  • E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
  • Year:
  • 2013

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Abstract

The power wall is one of the primary stumbling blocks that many-core microprocessor architecture is facing today. To avoid this problem, microprocessor makers are shifting towards heterogeneous chips that integrate different core architectures on a single die and that have proved to deliver better performance per watt. Moreover, these new hybrid microprocessors are equipped with dynamic frequency-scaling techniques that are capable of reducing total system power consumption. This paper presents a theoretical study on how performance and power consumption are affected by the dynamic frequency-scaling techniques offered by the power constraints imposed on state-of-the-art dual-architecture processors. Analytical schemes have been developed to extend Amdahl's Law by accounting for energy limitations before examining the three processing schemes available to heterogeneous processors: symmetric, asymmetric, and simultaneous asymmetric. Analysis shows that by choosing the optimal chip configuration, power efficiency and energy savings can be increased considerably while keeping sacrifices in performance at tolerable levels.