Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
International Journal of High Performance Computing Applications
Understanding the future of energy-performance trade-off via DVFS in HPC environments
Journal of Parallel and Distributed Computing
The Journal of Supercomputing
Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy consumption modeling for hybrid computing
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Heterogeneity-Aware optimal power allocation in data center environments
ICPCA/SWS'12 Proceedings of the 2012 international conference on Pervasive Computing and the Networked World
Multi-objective aware extraction of task-level parallelism using genetic algorithms
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Modeling the effects of DFS on power consumption in hybrid chip multiprocessors
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
Journal of Parallel and Distributed Computing
Analytical modeling of energy efficiency in heterogeneous processors
Computers and Electrical Engineering
Amdahl's law in the era of process variation
International Journal of High Performance Systems Architecture
Energy-efficient scheduling in multi-core servers
Computer Networks: The International Journal of Computer and Telecommunications Networking
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This paper derives simple, yet fundamental formulas to describe the interplay between parallelism of an application, program performance, and energy consumption. Given the ratio of serial and parallel portions in an application and the number of processors, we derive optimal frequencies allocated to the serial and parallel regions in an application to either minimize the total energy consumption or minimize the energy-delay product. The impact of static power is revealed by considering the ratio between static and dynamic power and quantifying the advantages of adding to the architecture capability to turn off individual processors and save static energy. We further determine the conditions under which one can obtain both energy and speed improvement, as well as the amount of improvement. While the formulas we obtain use simplifying assumptions, they provide valuable theoretical insights into energy-aware processor resource management. Our results form a basis for several interesting research directions in the area of energy-aware multicore processor architectures.