Next generation embedded processor architecture for personal information devices

  • Authors:

  • In-Pyo Hong;Yong-Joo Lee;Yong-Surk Lee

  • Affiliations:

  • The School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;The School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea;The School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea

  • Venue:
  • EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
  • Year:
  • 2006

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Abstract

In this paper, we proposed a processor architecture that is suitable for next generation embedded applications, especially for personal information devices such as smart phones, PDAs, and handheld computers. Latest high performance embedded processors are developed to achieve high clock speed. Because increasing performance makes design more difficult and induces large overhead, architectural evolution in embedded processor field is necessary. Among more enhanced processor types, out-of-order superscalar cannot be a candidate for embedded applications due to its excessive complexity and relatively low performance gain compared to its overhead. Therefore, new architecture with moderate complexity must be designed. In this paper, we developed a low-cost SMT architecture model and compared its performance to other architectures including scalar, superscalar and multiprocessor. Because current personal information devices have a tendency to execute multiple tasks simultaneously, SMT or CMP can be a good choice. And our simulation result shows that the efficiency of SMT is the best among the architectures considered