Modeling and analysis of core-centric network processors

Authors:
Yi-Neng Lin;Ying-Dar Lin;Yuan-Cheng Lai;Kuo-Kun Tseng
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;National Taiwan University of Science and Technology, Taipei, Taiwan;National Chiao Tung University, Hsinchu, Taiwan
Venue:
ACM Transactions on Embedded Computing Systems (TECS)
Year:
2008

Citing 9
Cited 0

Network Processors

Network Processors
Optimization and Benchmark of Cryptographic Algorithms on Network Processors

IEEE Micro
VPN Gateways over Network Processors: Implementation and Evaluation

RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Performance Models for Network Processor Design

IEEE Transactions on Parallel and Distributed Systems
Resource allocation in network processors for network intrusion prevention systems

Journal of Systems and Software
An overview of the Sam CMT simulator kit

An overview of the Sam CMT simulator kit
CPN tools for editing, simulating, and analysing coloured Petri nets

ICATPN'03 Proceedings of the 24th international conference on Applications and theory of Petri nets
DiffServ edge routers over network processors: implementation and evaluation

IEEE Network: The Magazine of Global Internetworking

Quantified Score

Hi-index	0.00

Visualization

Abstract

Network processors can be categorized into two types, the coprocessors-centric model in which data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, research regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation, we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single-process programming, since context-switch overhead impacts considerably on the performance.