VPN Gateways over Network Processors: Implementation and Evaluation

Authors:
Yi-Neng Lin;Chiuan-Hung Lin;Ying-Dar Lin;Yuan-Chen Lai
Affiliations:
National Chiao-Tung University, Hsinchu, Taiwan;National Chiao-Tung University, Hsinchu, Taiwan;National Chiao-Tung University, Hsinchu, Taiwan;National Taiwan University of Science and Technology, Taipei, Taiwan
Venue:
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Year:
2005

Citing 0
Cited 4

Modeling and analysis of core-centric network processors

ACM Transactions on Embedded Computing Systems (TECS)
Modeling and analysis of core-centric network processors

ACM Transactions on Embedded Computing Systems (TECS)
Thread allocation in CMP-based multithreaded network processors

Parallel Computing
A clustering and traffic-redistribution scheme for high-performance IPsec VPNs

HiPC'05 Proceedings of the 12th international conference on High Performance Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.