Proceedings of the 39th annual Design Automation Conference
A fully-programmable memory management system optimizing queue handling at multi gigabit rates
Proceedings of the 40th annual Design Automation Conference
Efficient use of memory bandwidth to improve network processor throughput
Proceedings of the 30th annual international symposium on Computer architecture
IBM PowerNP network processor: Hardware, software, and applications
IBM Journal of Research and Development
Queue Management in Network Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Overcoming the memory wall in packet processing: hammers or ladders?
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
A Study of Shared Buffer Memory Segmentation for Packet Switched Networks
AICT-ICIW '06 Proceedings of the Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services
Buffer allocation for advanced packet segmentation in Network Processors
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
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Memory subsystem performance is rapidly becoming an important bottleneck in network processing, partially because packets must be segmented to prevent memory fragmentation. Depending on segment length, accesses to memory are short and thus inefficient or long and hence storing efficiency drops. Besides, segments have one-to-one associated descriptors which require a large control buffer and high management effort to update them. Our contribution consists in allowing multiple segment lengths for packet segmentation even for a single packet. We propose two new segmentation algorithms that ensure a minimum number of segments, so as to achieve maximum packet throughput, while maintaining a high level of memory efficiency together with reducing the amount of control resources needed. Both algorithms are evaluated using a variety of packet traces and realistic system configurations in order to determine how different choices impact the performance and the storage efficiency. The findings were then used to realize the SmartMem Buffer Manager in VHDL, which was tested in a Virtex-4 FPGA and its performance measured to verify the simulation results and validate the higher performance of the proposed algorithms.