Proceedings of the 39th annual Design Automation Conference
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
Processing and Scheduling Components in an Innovative Network Processor Architecture
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Software Processing Performance in Network Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
PRO3: A Hybrid NPU Architecture
IEEE Micro
Queue Management in Network Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Design of an efficient memory subsystem for network processor
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Advanced packet segmentation and buffering algorithms in network processors
Transactions on High-Performance Embedded Architectures and Compilers IV
PARDIS: a programmable memory controller for the DDRx interfacing standards
Proceedings of the 39th Annual International Symposium on Computer Architecture
A programmable memory controller for the DDRx interfacing standards
ACM Transactions on Computer Systems (TOCS)
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Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queueing is desirable. In this paper we describe the architecture of a memory manager that can provide up to 10Gbs of aggregate throughput while handling 512K queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable embedded system, particularly network SoCs that implement per flow queuing. When designing this scheme several optimisation techniques have been evaluated and the most cost and performance effective ones used. These techniques minimize both the memory bandwidth and the memory capacity needed, which is considered a main advantage of the proposed scheme. The proposed architecture uses a simple DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimising the system's cost. The device has been fabricated within a novel programmable network processor designed for efficient protocol processing in high speed networking applications. It consists of 155K Gates and occupies 5.23 mm in UMC 0.18υ CMOS.