Efficient fair queueing using deficit round-robin
IEEE/ACM Transactions on Networking (TON)
Design issues for high-performance active routers
IEEE Journal on Selected Areas in Communications
A fully-programmable memory management system optimizing queue handling at multi gigabit rates
Proceedings of the 40th annual Design Automation Conference
Software Processing Performance in Network Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Towards a deep-packet-filter toolkit for securing legacy resources
LISA '05 Proceedings of the 19th conference on Large Installation System Administration Conference - Volume 19
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In this paper, we describe the architecture of aninnovative network processor aiming at the accelerationof packet processing in high speed network interfacesand at the tight coupling of low and high level protocols.The proposed design uses programmable hard-wiredcomponents with line rate throughput and is capable ofexecuting protocols and handling efficiently high andlow level streaming operations. We discuss the details ofthe main innovation of the proposed design, whichincorporates a three stage RISC-based pipelined moduleand a composite scheduling unit for internal resourcemanagement and outgoing traffic shaping. When bothcomponents are integrated on the same platform thenmaximum and fair utilization of the available resourcesis achieved. Quantitative performance results are given,both by means of microcode profiling and simulation forindicative applications of the protocol processor.