Network processors: flexibility and performance for next-generation networks
ACM SIGCOMM Computer Communication Review
An effective feedback control mechanism for Diffserv architecture
Journal of Computer Science and Technology
Design Tradeoffs for Embedded Network Processors
ARCS '02 Proceedings of the International Conference on Architecture of Computing Systems: Trends in Network and Pervasive Computing
Processing and Scheduling Components in an Innovative Network Processor Architecture
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Balancing performance and flexibility with hardware support for network architectures
ACM Transactions on Computer Systems (TOCS)
Automated tools to implement and test Internet systems in reconfigurable hardware
ACM SIGCOMM Computer Communication Review
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
High speed routers design using reconfigurable technology
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
Gridsat architecture: a step further towards security and efficiency
PDCN'06 Proceedings of the 24th IASTED international conference on Parallel and distributed computing and networks
High-speed routers design using data stream distributor unit
Journal of Network and Computer Applications - Special issue: Network and information security: A computational intelligence approach
Bridging undergraduate learning and research in software and hardware
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
Adaptive load sharing for network processors
IEEE/ACM Transactions on Networking (TON)
MOTIM: an industrial application using nocs
Proceedings of the 21st annual symposium on Integrated circuits and system design
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thread allocation in CMP-based multithreaded network processors
Parallel Computing
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
A case for dual-mapping one-way caches
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Queue - Large-Scale Implementations
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Modern networks require the flexibility to support new protocols and network services without changes in the underlying hardware. Routers with general-purpose processors can perform data path packet processing using software that is dynamically distributed. However, custom processing of packets at link speeds requires immense computational power. This paper proposes a design of a scalable, high-performance active router. Multiple network processors with cache and memory on a single application specific integrated circuit are used to overcome the limitations of traditional single processor systems. The proposed design is used as a vehicle for studying the key issues that must be resolved to allow active networking to become a mainstream technology. Benchmark measurements are used to put the design in relation to actual application demands