A case for dual-mapping one-way caches

Authors:
Arul Sandeep Gade;Yul Chu
Affiliations:
Department of Electrical and Computer Engineering, Mississippi State University, MS;Department of Electrical and Computer Engineering, Mississippi State University, MS
Venue:
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Year:
2006

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Abstract

This paper proposes a dual-mapping function for one-way data cache to reduce cache misses, write-back rates, and access time for single-core or multi-core computing processors. Our simulation results show that it reduces cache misses significantly compared to any conventional L1 caches. Simple Scalar simulator has been used for these simulations with SPEC95FP and Minne SPEC2000FP benchmark programs. In addition, it has a simple hardware complexity similar to that of a 2-way SAC (set-associative cache). The proposed cache has good AMAT (average memory access time) compared to a 2-way cache and also uses fewer execution cycles. Simulations over CACTI were performed to evaluate the hardware implications as well.