A parallel simulator for network terminal packet buffer

Authors:
Yul Chu;Jin Hwan Park;Yan Bai;Jae Sok Son;Sanjeev Kumar
Affiliations:
Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA;Department of Computer Science, California State University, Fresno, CA, USA;Institute of Technology, University of Washington, Tacoma, WA, USA;Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA;Department of Electrical Engineering, University of Texas Pan American, Edinburg, TX, USA
Venue:
Simulation
Year:
2012

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Abstract

In this paper we present the design and implementation of a parallel network simulator to manipulate the shared-memory packet buffer in a network interface card (NIC) for a network terminal. The proposed simulator consists of two components, input generator and buffer management simulator. The simulator flexibly accommodates either a dynamic or a static packet buffer management algorithm for a high-speed Ethernet to deliver fast and accurate clock-cycle level data analysis. In addition, it is transparent to trace and analyze the concurrent operations in the packet buffer and, thus, the simulator contributes to developing efficient buffer management algorithms.