Embedded Protocol Processor for Fast and Efficient Packet Reception

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Venue:
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Year:
2002

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Abstract

Computer networks equipment present a bottleneck for further increase of the capacity in the networks. The terminals have problems to keep up with the network speed when using general purpose processors for the protocol processing. We present a novel processor architecture, that works in-line with the data flow and does not use a traditional von Neuman architecture. The program is contained in three lookup tables within the processor core, whichallows for one cycle if-then-else and switch-case-case... execution. The processor is estimated to be able to handle a 10 Gb/s Ethernet connection when implemented in a 0.18 micron technology.