Dynamic queue length thresholds for shared-memory packet switches
IEEE/ACM Transactions on Networking (TON)
Embedded Protocol Processor for Fast and Efficient Packet Reception
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
An Enhanced Dynamic Packet Buffer Management
ISCC '05 Proceedings of the 10th IEEE Symposium on Computers and Communications
Buffer management for shared-memory ATM switches
IEEE Communications Surveys & Tutorials
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This paper proposes a dynamic shared-memory packet buffer management algorithm for a protocol processor in a network terminal. The protocol processor is located in a network interface card (NIC). In general, two types of packet buffer management algorithms, static and dynamic, can be used in a NIC; the dynamic buffer management algorithms work better than the static ones for reducing the packet loss ratio. However, conventional dynamic buffer management algorithms do not provide even packet losses to all the applica-tions. Therefore, we propose an algorithm to enhance even packet losses and the proposed algorithm improves the packet loss ratio by 11.80% to 16.70% compared to other conventional dynamic algorithms.