Competitve buffer management for shared-memory switches
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Scheduling policies for CIOQ switches
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
State Space Merging Approach to Optimization of Push-Out Strategies in Packet Switching Networks
Cybernetics and Systems Analysis
Harmonic buffer management policy for shared memory switches
Theoretical Computer Science - Special issue: Online algorithms in memoriam, Steve Seiden
Cybernetics and Systems Analysis
Competitive buffer management for shared-memory switches
ACM Transactions on Algorithms (TALG)
A Dynamic Packet Management in a Protocol Processor
ICCSA '09 Proceedings of the International Conference on Computational Science and Its Applications: Part II
Wireless Personal Communications: An International Journal
A shared-memory packet buffer management in a network interface card
APNOMS'06 Proceedings of the 9th Asia-Pacific international conference on Network Operations and Management: management of Convergence Networks and Services
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In the shared-memory switch architecture, output links share a single large memory, in which logical FIFO queues are assigned to each link. Although memory sharing can provide a better queuing performance than physically separated buffers, it requires carefully designed buffer management schemes for a fair and robust operation. This article presents a survey of the buffer management methods that have been proposed for shared-memory packet switches. Several buffer management policies are described, and their strengths and weaknesses are examined. The performances of various policies are evaluated using computer simulations. A comparison of the most important schemes is obtained with the help of the simulation results and the results provided in the literature. The survey concludes with a discussion of the possible future research areas related to shared-memory ATM switches.