ACM Computing Surveys (CSUR)
Communications of the ACM
Embedded Protocol Processor for Fast and Efficient Packet Reception
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Analysis of a reconfigurable network processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.