Network Systems Design Using Network Processors
Network Systems Design Using Network Processors
DynaCORE — A Dynamically Reconfigurable Coprocessor Architecture for Network Processors
PDP '06 Proceedings of the 14th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Digital Design: Principles and Practices Package (4th Edition)
Digital Design: Principles and Practices Package (4th Edition)
Computer Networks: The International Journal of Computer and Telecommunications Networking
NetFPGA—An Open Platform for Teaching How to Build Gigabit-Rate Network Switches and Routers
IEEE Transactions on Education
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
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Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at register-transfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based high-speed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with today's field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.